1. Field of the Invention
The present invention relates to an error detecting device, an error detection method and a control system and, more particularly, to an error detecting device, an error detection method and a control system for detecting an occurrence of a data error (garbled data) in a register which temporarily stores data to be calculated or a calculated result.
2. Description of the Relevant Art
Garbled data is sometimes caused in a register by a power failure or noise. If the processing is continued as usual in spite of the occurrence of garbled data in the register, there is a possibility that the electronic equipment itself may be damaged. Therefore, it is extremely important to detect the occurrence of garbled data in the register.
For that reason, hitherto, various kinds of methods for detecting garbled data in a register have been proposed (e.g. see the below-mentioned Patent Document 1). FIG. 6 is a block diagram schematically showing the principal part of a conventional error detecting device for detecting garbled data in a register. The conventional error detecting device comprises a state hold register 1 for holding input data, an inverter circuit (NOT circuit) 2 for inverting and outputting the input data, a reference register 3 for holding the data from the inverter circuit 2, an inverter circuit 4 for inverting and outputting the data from the state hold register 1, an NAND circuit 5 for receiving the data from the inverter circuit 4 and the data from the reference register 3, and operating and outputting a ‘negated AND’, and an EX-OR circuit 6 for receiving the data from the inverter circuit 4 and the data from the reference register 3, and operating and outputting an ‘exclusive-OR’ (that is, deciding the correctness of the data held in the state hold register 1 and outputting an error flag).
A data control signal is a signal for permitting to write data into the state hold register 1 and the reference register 3. The state hold register 1 holds the input data when receiving the data control signal which permits the writing of data. The reference register 3 holds the data from the inverter circuit 2 (the inverted data of the input data) when receiving the data control signal.
A detecting operation of an occurrence of a data error performed with a data holding operation in this error detecting device is described below. First, a case of no occurrence of a data error is described. When an input signal data into the state hold register 1 is ‘0’, and the state hold register 1 and the reference register 3 receive a data control signal of ‘1’, the state hold register 1 holds the data ‘0’ and the reference register 3 holds the data ‘1’.
In this situation, the data ‘1’ from the inverter circuit 4 and the data ‘1’ from the reference register 3 are output to the NAND circuit 5 and the EX-OR circuit 6. Accordingly, the data ‘0’ (the same as the data held in the state hold register 1) is output from the NAND circuit 5, while the data ‘0’ is output from the EX-OR circuit 6 as an error flag. When a data error occurs, the error flag turns ‘1’.
Next, a case of an occurrence of a data error is described. When the data held in the state hold register 1 is transformed from ‘0’ to ‘1’ due to an instantaneous power interruption and the like, the data ‘0’ from the inverter circuit 4 and the data ‘1’ from the reference register 3 are output to the EX-OR circuit 6, leading to outputting of the data ‘1’ from the EX-OR circuit 6 as an error flag. Thus, the occurrence of a data error can be detected.
However, in this conventional error detecting device, in order to detect an occurrence of a data error in one register (state hold register 1), another register (reference register 3) is required, that is, a double-register construction is needed, resulting in a great increase in cost. In addition, when the scale of a digital circuit is huge, the double-register construction is extremely difficult to realize with consideration of arrangement space and the like.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2004-13196